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universal single-chip clock solution for via p4m266/km266 ddr systems CY28341 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-07367 rev. *a revised december 26, 2002 features ? supports via ? p4m266/km266 chipsets supports pentium? 4, athlon? processors supports two ddr dimms supports three sdrams dimms at 100 mhz provides: ? two different programmable cpu clock pairs ? six differential sdram ddr pairs ? three low-skew/low-jitter agp clocks ? seven low-skew/low-jitter pci clocks ? one 48m output for usb ? one programmable 24m or 48m for sio dial-a-frequency? and dial-a-db ? features spread spectrum for best electromagnetic interference (emi) reduction watchdog feature for systems recovery smbus-compatible for programmability 56-pin ssop and tssop packages note: 1. pins marked with [*] have internal pull-up resistors. pins marked with [**] have internal pull-down resistors. table 1. frequency selection table fs(3:0) cpu agp pci 0000 66.80 66.80 33.40 0001 100.00 66.80 33.40 0010 120.00 60.00 30.00 0011 133.33 66.67 33.33 0100 72.00 72.00 36.00 0101 105.00 70.00 35.00 0110 160.00 64.00 32.00 0111 140.00 70.00 35.00 1000 77.00 77.00 38.50 1001 110.00 73.33 36.67 1010 180.00 60.00 30.00 1011 150.00 60.00 30.00 1100 90.00 60.00 30.00 1101 100.00 66.67 33.33 1100 200.00 66.67 33.33 1111 133.33 66.67 33.33 block diagram pin configuration [ 1 ] pll1 s2d convert smbus wd cpucs_t/c vddc vddi cpu(0:1)/cpu0d_t/c selp4_k7# pci(3:6) pci_f fs1 ref(0:1) vddr fs0 48m 24_48m fbout ddrt(0:5)/sdram(0,2,4,6,8,10) sclk sdata pd# agp(0:2) vddagp vdd48m vddd xtal xout xin fs2 pci2 pci1 vddpci pll2 sreset# / 2 buf_in ref0 fs3 multsel selsdr_ddr ddrc(0:5)/sdram(1,3, 5,7,9,11) wden 56 pin ssop vssr *fs0/ref0 xin xout vddagp agp0 *selp4_k7/agp1 vssagp agp2 **selsdr_ddr/pci1 *multsel/pci2 vsspci pci3 pci4 vddpci pci5 pci6 vss48m **fs3/48m **fs2/24_48m vdd48m vdd vss iref *pd#/sreset# sclk sdata **fs1/pci_f vddr vttpwrgd#/ref1 vssc cput/cpuod_t cpuc/cpuod_c vddc vddi cpucs_t cpucs_c fbout buf_in ddrt0/sdram0 ddrc0/sdram1 ddrt1/sdram2 ddrc1/sdram3 vddd vssd ddrt2/sdram4 ddrc2/sdram5 ddrt3/sdram6 ddrc3/sdram7 vddd vssd ddrt4/sdram8 ddrc4/sdram9 ddrt5/sdram10 ddrc5/sdram11 vssi CY28341 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
CY28341 document #: 38-07367 rev. *a page 2 of 21 pin description [2] pin name pwr i/o description 3xin i oscillator buffer input . connect to a crystal or to an external clock. 4 xout vdd o oscillator buffer output . connect to a crystal. do not connect when an external clock is applied at x in . 1 fs0/ref0 vdd i/o pu power-on bidirectional input/output . at power-up, fs0 is the input. when the power supply voltage crosses the input threshold voltage, fs0 state is latched and this pin becomes ref0, buffered copy of signal applied at xin. 56 vttpwrgd# vddr i if selp4_k7 = 1, with a p4 processor setup as cput/c. at power-up, vtt_pwrgd# is an input. when this input transitions to a logic low, the fs (3:0) and multsel are latched and all output clocks are enabled. after the first high to low transition on vtt_pwrgd#, this pin is ignored and will not effect the behavior of the device thereafter. when the vtt_pwrgd# feature is not used, please connect this signal to ground through a 10k ? resistor. ref1 vddr o if selp4_k7 = 0, with an athlon (k7) processor as cpu_od(t:c). vtt_pwrgd# function is disabled, and the feature is ignored. this pin becomes ref1 and is a buffered copy of the signal applied at x in . 44,42,38, 36,32,30 ddrt (0:5)/sdram(0,2,4,6, 8,10) vddd o these pins are programmable through strapping pin11, selsdr_ddr#.if selsdr_ddr#.= 0, these pins are configured for ddr clock outputs. they are ? true ? copies of signal applied at pin45, buf_in. in this mode, vddd must be 2.5vif selsdr_ddr#.= 1, these pins are configured for sdram(0,2,4,6,8,10) single ended clock outputs, copies of (and in phase with) signal applied at pin45, buf_in. in this mode, vddd must be 3.3v 43,41,37 35,31,29 ddrc (0:5)/sdram(1,3,5,7, 9,11) vddd o these pins are programmable through strapping pin11, selsdr_ddr#.if selsdr_ddr#.= 0, these pins are configured for ddr clock outputs. they are ? complementary ? copies of signal applied at pin45, buf_in. in this mode, vddd must be 2.5vif selsdr_ddr#.= 1, these pins are configured for sdram(1,3,5,7,9,11) single-ended clock outputs, copies of (and in phase with) signal applied at pin45, buf_in. in this mode, vddd must be 3.3v. 7 selp4_k7 / agp1 vddag p i/o pu power-on bidirectional input/output . at power-up, selp4_k7 is the input. when the power supply voltage crosses the input threshold voltage, selp4_k7 state is latched and this pin becomes agp1 clock output. selp4_k7 = 1, p4 mode. selp4_k7 = 0, k7 mode. 12 multsel / pci2 vddpci i/o pu power-on bidirectional input/output . at power-up, multsel is the input. when the power supply voltage crosses the input threshold voltage, multsel state is latched and this pin becomes pci2 clock output. multsel = 0, ioh is 4 x irefmultsel = 1, ioh is 6 x iref. 53 cput/cpuod_t vddc o 3.3v cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7. if selp4_k7 = 1, this pin is configured as the cput clock output. if selp4_k7 = 0, this pin is configured as the cpuod_t open drain clock output. see table 1 . 52 cpuc/cpuod_c vddc o 3.3v cpu clock outputs . this pin is programmable through strapping pin7, selp4_k7. if selp4_k7 = 1, this pin is configured as the cpuc clock output. if selp4_k7 = 0, this pin is configured as the cpuod_c open drain clock output. see table 1 . 48,49 cpucs_t/c vddi o 2.5v cpu clock outputs for chipset . see table 1 . 14,15,17, 18 pci (3:6) vddpci o pci clock outputs . are synchronous to cpu clocks. see table 1 . 10 fs1/pci_f vddpci i/o pd power-on bidirectional input/output . at power-up, fs0 is the input. when the power supply voltage crosses the input threshold voltage, fs1 state is latched and this pin becomes pci_f clock output. 20 fs3/48m vdd48m i/o pd power-on bidirectional input/output . at power-up, fs3 is the input. when the power supply voltage crosses the input threshold voltage, fs3 state is latched and this pin becomes 48m, a usb clock output.
CY28341 document #: 38-07367 rev. *a page 3 of 21 note: 2. pu = internal pull-up. pd = internal pull-down. typically = 250 kw (range 200 kw to 500 kw). 11 selsdr_ddr#/pci 1 vddpci i/o pd power-on bidirectional input/output . at power-up, selsdr_ddr is the input. when the power supply voltage crosses the input threshold voltage, selsdr_ddr state is latched and this pin becomes pci clock output.selsdr_ddr#. = 0, ddr mode. selsdr_ddr#. = 1, sdr mode. 21 fs2/24_48m vdd48m i/o pd power-on bidirectional input/output . at power-up, fs2 is the input. when the power supply voltage crosses the input threshold voltage, fs2 state is latched and this pin becomes 24_48m, a sio programmable clock output. 6 agp0 vddag p o agp clock output . is synchronous to cpu clocks. see table 1 . 8 agp2 vddag p o agp clock output . is synchronous to cpu clocks. see table 1 . 25 iref i current reference programming input for cpu buffers. a precise resistor is attached to this pin, which is connected to the internal current reference. 28 sdata i/o serial data input . conforms to the philips i2c specification of a slave receive/transmit device. it is an input when receiving data. it is an open drain output when acknowledging or transmitting data. 27 sclk i serial clock input . conforms to the philips i2c specification. 26 pd#/sreset# i/o pu power-down input/system reset control output . if byte6 bit7 = 0, this pin becomes a sreset# open drain output, and the internal pulled up is not active. see system reset description. if byte6 bit7 = 1 (default), this pin becomes pd# input with an internal pull-up. when pd# is asserted low, the device enters power-down mode. see power management function. 45 buf_in if selsdr_ddr#.= 0, 2.5v cmos type input to the ddr differential buffers.if selsdr_ddr#.= 1, 3.3v cmos type input to the sdr buffer. 46 fbout if selsdr_ddr#.= 0, 2.5v single ended sdram buffered output of the signal applied at buf_in. it is in phase with the ddrt(0:5) signals.if selsdr_ddr#.= 1, 3.3v single ended sdram buffered output of the signal applied at buf_in. it is in phase with the sdram(0:11) signals 5 vddagp 3.3v power supply for agp clocks 51 vddc 3.3v power supply for cput/c clocks 16 vddpci 3.3v power supply for pci clocks 55 vddr 3.3v power supply for ref clock 50 vddi 2.5v power supply for cpucs_t/c clocks 22 vdd48m 3.3v power supply for 48m 23 vdd 3.3v common power supply 34,40 vddd if selsdr_ddr#.= 0, 2.5v power supply for ddr clocksif selsdr_ddr#.= 1, 3.3v power supply for sdr clocks. 9 vssagp ground for agp clocks 13 vsspci ground for pci clocks 54 vssc ground for cput/c clocks 33,39 vssd ground for ddr clocks 19 vss48m ground for 48m clock 47 vssi ground for icpucs_t/c clocks 24 vss common ground pin description [2] (continued) pin name pwr i/o description
CY28341 document #: 38-07367 rev. *a page 4 of 21 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individual indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 , while table 4 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 2. command code definition bit description 7 0 = block read or block write operation 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for block read or block write operations, these bits should be ? 0000000 ? table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ? 00000000 ? stands for block operation 11:18 command code ? 8-bit ? 00000000 ? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop
CY28341 document #: 38-07367 rev. *a page 5 of 21 serial control registers table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ? 1xxxxxxx ? stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits ? 1xxxxxxx ? stands for byte operationbit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop byte 0: frequency select register bit @pup pin# name description 7 0 reserved reserved 6 h/w setting 21 fs2 for selecting frequencies see table 1 . 5 h/w setting 10 fs1 for selecting frequencies see table 1 . 4 h/w setting 1 fs0 for selecting frequencies see table 1 . 3 0 if this bit is programmed to ? 1, ? it enables write to bits (6:4,1) for selecting the frequency via software (smbus). if this bit is programmed to a ? 0, ? it enables only read of bits (6:4,1), which reflects the hardware setting of fs(0:3). 2 h/w setting 11 selsdr_ddr only for reading the hardware setting of the sdram interface mode, status of selsdr_ddr# strapping. 1 h/w setting 20 fs3 for selecting frequencies see table 1 . 0 h/w setting 7 selp4_k7 only for reading the hardware setting of the cpu interface mode, status of selp4_k7# strapping. byte 1: cpu clocks register bit @pup pin# name description 7 0 mode 0 = down spread. 1 = center spread. see table 9. 6 1 sscg 1 = enable (default). 0 = disable 5 1 sst1 select spread bandwidth. see table 9 . 4 1 sst0 select spread bandwidth. see table 9 . 3 1 48,49 cpucs_t, cpucs_c 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 53,52 cput/cpuod_t cpuc/cpuod_c 1 = output enabled (running). 0 = output disable. 1 1 53,52 cput/c in k7 mode, this bit is ignored.in p4 mode, 0 = when pd# asserted low, cput stops in a high state, cpuc stops in a low state. in p4 mode, 1 = when pd# asserted low, cput and cpuc stop in high-z. 0 1 11 mult0 only for reading the hardware setting of the pin11 mult0 value.
CY28341 document #: 38-07367 rev. *a page 6 of 21 byte 2: pci clock register bit @pup pin# name description 7 0 pci_drv pci clock output drive strength 0 = normal, 1 = increase the drive strength 20%. 6 1 10 pci_f 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 18 pci6 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 1 17 pci5 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 3 1 15 pci4 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 14 pci3 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 12 pci2 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 11 pci1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. byte 3 : agp/peripheral clocks register bit @pup pin# name description 7 0 21 24_48m ? 0 ? = pin21 output is 24mhz. writing a ? 1 ? into this register asynchronously changes the frequency at pin21 to 48 mhz. 6 1 20 48mhz 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 21 24_48m 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 0 6,7,8 dasag1 programming these bits allow shifting skew of the agp(0:2) signals relative to their default value. see table 5 . 3 0 6,7,8 dasag0 2 1 8 agp2 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 7 agp1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 6 agp0 1 = output enabled (running). 0 = output disabled asynchronously in a low state. table 5. dial-a-skew ? agp(0:2) dasag (1:0) agp(0:2) skew shift 00 default 01 ? 280 ps 10 +280 ps 11 +480 ps byte 4 : peripheral clocks register bit @pup pin# name description 7 1 20 48m 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength 6 1 21 24_48m 1 = normal strength, 0 = high strength 1 = normal strength, 0 = high strength 5 0 6,7,8 darag1 programming these bits allow modifying the frequency ratio of the agp(2:0), pci(6:1, f) clocks relative to the cpu clocks. see table 6 . 4 0 6,7,8 darag0 3 1 1 ref0 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 56 ref1 1 = output enabled (running). 0 = output disabled asynchronously in a low state. (k7 mode only.) 1 1 1 ref0 1 = normal strength, 0 = high strength 0 1 56 ref1 1 = normal strength, 0 = high strength (k7 mode only.) table 6. dial-a-ratio ? agp(0:2) darag (1:0) cu/agp ratio 00 frequency selection default 01 2/1 10 2.5/1 11 3/1
CY28341 document #: 38-07367 rev. *a page 7 of 21 byte 5 : sdr/ddr clock register bit @pup pin# name description 70 45 buf_in threshold voltage ddr mode, buf_in threshold setting. 0 = 1.15v, 1 = 1.05vsdr mode, buf_in threshold setting. 0 = 1.35v, 1 = 1.25v 6 1 46 fbout 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 5 1 29,30 ddrt/c5/sd ram(10,11) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 4 1 31,32 ddrt/c4/sd ram(8,9) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 3 1 35,36 ddrt/c3/sd ram(6,7) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 2 1 37,38 ddrt/c2/sd ram(4,5) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 1 1 41,42 ddrt/c1/sd ram(2,3) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. 0 1 43,44 ddrt/c0/sd ram(0,1) 1 = output enabled (running). 0 = output disabled asynchronously in a low state. byte 6: watchdog register bit @pup pin# name description 7 1 26 sreset# 1 = pin 26 is the input pin as pd# signal. 0 = pin 26 is the output pin as sreset# signal. 6 0 frequency revert this bit allows setting the revert frequency once the system is rebooted due to watchdog time out only.0 = selects frequency of existing h/w setting1 = selects frequency of the second to last s/w setting (the software setting prior to the one that caused a system reboot). 5 0 wdtest wd-test, always program to ? 0. ? 4 0 wd alarm this bit is set to ? 1 ? when the watchdog times out. it is reset to ? 0 ? when the system clears the wd time stamps (wd3:0). 3 0 wd3 this bit allows the selection of the time stamp for the watchdog timer. see table 7 . 2 0 wd2 this bit allows the selection of the time stamp for the watchdog timer. see table 7 . 1 0 wd1 this bit allows the selection of the time stamp for the watchdog timer. see table 7 . 0 0 wd0 this bit allows the selection of the time stamp for the watchdog timer. see table 7 . table 7. watchdog time stamp wd3 wd2 wd1 wd0 function 00 0 0off 0 0 0 1 1 second 0 0 1 0 2 seconds 0 0 1 1 3 seconds 0 1 0 0 4 seconds 0 1 0 1 5 seconds 0 1 1 0 6 seconds 0 1 1 1 7 seconds 1 0 0 0 8 seconds 1 0 0 1 9 seconds 1 0 1 0 10 seconds 1 0 1 1 11 seconds 1 1 0 0 12 seconds 1 1 0 1 13 seconds 1 1 1 0 14 seconds 1 1 1 1 15 seconds
CY28341 document #: 38-07367 rev. *a page 8 of 21 dial-a-frequency feature smbus dial-a-frequency feature is available in this device via byte7 and byte9. p is a pll constant that depends on the frequency selection prior to accessing the dial-a-frequency feature. spread spectrum clock generation (sscg) spread spectrum is enabled/disabled via smbus register byte 1, bit 7. byte 7: dial-a-frequency control register n bit @pup pin# name description 7 0 reserved reserved for device function test. 6 0 n6, msb these bits are for programming the pll ? s internal n register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50 n5 40 n4 30 n3 20 n2 10 n3 00 n0, lsb byte 8: silicon signature register (all bits are read-only) bit @pup pin# name description 7 0 revision_id3 revision id bit [3] 6 0 revision_id2 revision id bit [2] 5 0 revision_id1 revision id bit [1] 4 0 revision_id0 revision id bit [0] 3 1 vender_id3 cypress vender id bit [3]. 2 0 vender_id2 cypress vender id bit [2]. 1 0 vender_id1 cypress vender id bit [1]. 0 0 vender_id0 cypress vender id bit [0]. byte9: dial-a-frequency control register r bit @pup pin# name description 70 reserved 6 0 r5, msb these bits are for programming the pll ? s internal r register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clocks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50 r4 40 r3 30 r2 20 r1 10 r0 0 0 daf_enb this edge-trigger bit enables the dial-a-frequency n and r bits. it is the transition of this bit from ? 0 ? to ? 1 ? that latches the n(6:0) and r(5:0) data into the internal n and r registers. the user must only program a one time ? 1 ? into this bit for every new n and r values table 8. fs(4:0) p xxxxx 96016000
CY28341 document #: 38-07367 rev. *a page 9 of 21 system self-recovery clock management this feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang-up due to the frequency change. when the system sends an smbus command requesting a frequency change through byte 4 or through bytes 13 and 14, it must have previously sent a command to byte 12, for selecting which time out stamp the watchdog must perform, otherwise the system self recovery feature will not be appli- cable. consequently, this device will change frequency and then the watchdog timer starts timing. meanwhile, the system bios is running its operation with the new frequency. if this device receives a new smbus command to clear the bits origi- nally programmed in byte 12,bits (3:0) (reprogram to 0000), before the watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. if the watchdog times out the first time before the new smbus reprograms byte12,bits (3:0) to (0000), then this device will send a low system reset pulse, on sreset# (see byte12,bit7), and changes wd alarm (byte12,bit4) status to ? 1 ? then restarts the watchdog timer again. if the watchdog times out a second time, then this device will send another low pulse on sreset#, will relatch original hardware strapping frequency (or second to last software selected frequency, see byte12,bit6) selection, set wd alarm bit (byte12,bit4) to ? 1, ? then start wd timer again. the above-described sequence will keep repeating until the bios clears the smbus byte12,bits(3:0). once the bios sets byte12,bits(3:0) = 0000, then the watchdog timer is turned off and the wd alarm bit (byte12,bit4) is reset to ? 0. ? power management functions all clocks can be individually enabled or stopped via the 2-wire control interface. all clocks are stopped in the low state. all clocks maintain a valid high period on transitions from running to stop and on transitions from stopped to running when the chip was not powered down. on power-up, the vcos will stabilize to the correct pulse widths within about 0.5 ms. table 9. spread spectrum table mode sst1 sst0 % spread 00 0 ? 1.5% 00 1 ? 1.0% 01 0 ? 0.7% 01 1 ? 0.5% 1 0 0 0.75% 10 1 0.5% 1 1 0 0.35% 1 1 1 0.25% swing select functions through hardware mult- sel board target trace/term z reference r, iref = vdd/(3*rr) output current voh@z 0 50 ohm rr = 221 1%, iref = 5.00 ma ioh = 4 * iref 1.0v@50 1 50 ohm rr = 475 1%, iref = 2.32 ma ioh = 6 * iref 0.7v@50 s ystem running w ith o rig in a lly s e le c te d frequency via h a rd w a re s tra p p in g . r eceive frequency c hange r equest via sm bus byte 4 or via dial- a-frequency? s ta rt in te rn a l w a tc h d o g tim e r. w atch d og tim e out? turn off w atch dog tim er. k e e p n e w fre q u e n c y s e ttin g . s e t w d a la rm bit (byte 12, bit4) to ?? 0 ? 1) s end another 3m s low pulse on sr ese t 2 ) r e la tc h o rig in a l h a rd w a re s tra p p in g s e le c tio n fo r re tu rn to o rig in a l fre q u e n c y s e ttin g s . 3 ) s e t w d a la rm b it (b y te 1 2 , b it4 ) to "1 " 4 ) s ta rt w d tim e r frequency w ill change but system self r ecovery not applicable (no tim e stam p selected and byte 12, bit(3:0) is still = "0000" no no yes no no yes sm bus byte 12 tim e out stam p disabled? is s m b u s b y te 9 , tim e o u t stam p enabled - (byte 12, bit (3 :0 ) 0 0 0 0 )? c hange to a new frequency yes 1) send sreset pulse 2) set w d bit (byte12, bit4) to ? 1 ? 3 ) s ta rt w d tim e r yes w a tc h d o g tim e o u t? no yes s m b u s b y te 9 tim e o u t stam p disabled, b yte 12, bit(3:0) = (0000)? yes no figure 1.
CY28341 document #: 38-07367 rev. *a page 10 of 21 maximum ratings [3] input voltage relative to v ss :.............................. v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature: ................................ ? 65 c to + 150 c operating temperature: .................................... 0 c to +70 c maximum esd .............................................................2000v maximum power supply: ................................................5.5v this device contains circuitry to protect inputs against damage due to high-static voltages or electric field. however, precau- tions should be take to avoid application of any voltage higher than the maximum-rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc parameters v dd = v ddpci = v ddagp = v ddr = v dd48m = v ddc = 3.3v 5%, v ddi = v dd = 2.5v 5%, t a = 0 c to +70 c parameter description conditions min. typ. max. unit vil1 input low voltage applicable to pd#, f s(0:4) 0.8 vdc vih1 input high voltage 2.0 vdc vil2 input low voltage applicable to sdata and sclk 1.0 vdc vih2 input high voltage 2.2 vdc vol output low voltage for sreset# i ol 0.4 v iol pull-down current for sreset# v ol = 0.4v 24 35 ma ioz three-state leakage current 10 a idd3.3v dynamic supply current cpu frequency set at 133.3 mhz [5] 150 190 ma idd2.5v dynamic supply current cpu frequency set at 133.3 mhz [5] 175 195 ma ipd power-down supply current pd# = 0 95 600 a ipup internal pull-up device current input @ v ss ? 25 a ipdwn internal pull-down device current input @ v dd 10 a cin input pin capacitance 5pf cout output pin capacitance 6pf lpin pin inductance 7pf cxtal crystal pin capacitance measured from the x in or x out to v ss 27 36 45 pf ac parameters parameter description 100 mhz 133mhz 200 mhz unit notes [4] min. max. min. max min. max xtal tdc x in duty cycle 45 55 45 55 45 55 % 7,8 tperiod x in period 69.841 71.0 69.84 71.0 69.84 71.0 ns 7,8 vhigh x in high voltage 0.7v dd v dd 0.7v dd v dd 0.7v dd v dd v9 vlow x in low voltage 0 0.3v dd 00.3v dd 00.3v dd v10 tr/tf x in rise and fall times 10.0 10 10 ns 10 tccj x in cycle to cycle jitter 500 500 500 ps 11,12 txs crystal start-up time 30 30 30 ms 12,9 p4 mode cpu at 0.7v tdc cput/c duty cycle 45 55 45 55 45 55 % 7,11,14,21, 22 tperiod cput/c period 9.85 10.2 7.35 7.65 4.85 5.1 ns 7,11,14,21, 22 tr/tf cput/c rise and fall times 175 700 175 700 175 700 ps 23,24 rise/fall matching 20% 20% 20% 23,26,24 delta tr/tf rise/fall time variation 125 125 125 ps 11,23,22 tskew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 ps 11,15,21,22 tccj cput/c cycle to cycle jitter ? 150 +150 ? 150 +150 ? 200 +200 ps 11,15,21,22 notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 4. all notes for this table may be found at the end of the table, on page 12.
CY28341 document #: 38-07367 rev. *a page 11 of 21 vcross crossing point voltage at 0.7v swing 280 430 280 430 280 430 mv 22 p4 mode cpu at 1.0v tdc cput/c duty cycle 45 55 45 55 45 55 % 11,14,21 tperiod cput/c period 9.85 10.2 7.35 7.65 4.85 5.1 ns 11,14,21 differential tr/tf cput/c rise and fall times 175 467 175 467 175 467 ps 13,15,25 tskew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 0 11,15,21 tccj cput/c cycle to cycle jitter ? 150 +150 ? 150 +150 ? 200 +200 ps 11,15,21 vcross crossing point voltage at 1v swing 510 760 510 760 510 760 mv 26 se- deltaslew absolute single-ended rise/fall waveform symmetry 325 325 325 ps 24,31 k7 mode tdc cpuod_t/c duty cycle 45 55 45 55 45 55 % 11,14 tperiod cpuod_t/c period 9.98 10.5 7.5 8.0 5 5.5 ns 11,14 tlow cpuod_t/c low time 2.8 1.67 2.8 ns 11,14 tf cpuod_t/c fall time 0.4 1.6 0.4 1.6 0.4 1.6 ns 11,13 tskew cpucs_t/c to cput/c clock skew 0 200 0 150 0 200 0 11,15,21 tccj cpuod_t/c cycle to cycle jitter ? 150 +150 ? 150 +150 ? 200 +200 ps 11,14 vd differential voltage ac 0.4 vp+.6v 0.4 vp+.6v 0.4 vp+.6v v 20 vx differential crossover voltage 500 1100 500 1100 500 1100 mv 19 chipset clock tdc cpucs_t/c duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod cpucs_t/c period 10.0 10.5 15 15.5 10.0 10.5 ns 7,11,14 tr / tf cpucs_t/c rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 ns 7,11,13 vd differential voltage ac 0.4 vp+.6v 0.4 vp+.6v 0.4 vp+.6v v 27 vx differential crossover voltage 0.5*v ddi ? 0.2 0.5*v ddi + 0.2 0.5*v ddi ? 0.2 0.5*v ddi + 0.2 0.5*v ddi ? 0.2 0.5*v ddi + 0.2 v21 agp tdc agp(0:2) duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod agp(0:2) period 15 16 15 16 15 16 ns 7,11,14 thigh agp(0:2) high time 5.25 5.25 5.25 ns 11,16 tlow agp(0:2) low time 5.05 5.05 5.05 ns 11,17 tr / tf agp(0:2) rise and fall times 0.4 1.6 0.4 1.6 0.4 1.6 ns 11,13 tskew any agp to any agp clock skew 250 250 250 ps 11,15 tccj agp(0:2) cycle to cycle jitter 500 500 500 ps 11,14,15 pci tdc pci(_f,1:6) duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod pci(_f,1:6) period 30.0 30.0 30.0 ns 7,11,14 thigh pci(_f,1:6) high time 12.0 12.0 12.0 ns 11,16 tlow pci(_f,1:6) low time 12.0 12.0 12.0 ns 11,17 tr / tf pci(_f,1:6) rise and fall times 0.5 2.5 0.5 2.5 0.5 2.5 ns 11,13 tskew any pci to any pci clock skew 500 500 500 ps 11,15 tccj pci(_f,1:6) cycle to cycle jitter 500 500 500 ps 11,14,15 48mhz tdc 48mhz duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod 48mhz period 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns 7,11,14 ac parameters (continued) parameter description 100 mhz 133mhz 200 mhz unit notes [4] min. max. min. max min. max
CY28341 document #: 38-07367 rev. *a page 12 of 21 tr / tf 48mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 11,13 tccj 48mhz cycle to cycle jitter 500 500 500 ps 11,14,15 24mhz tdc 24mhz duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod 24mhz period 41.660 41.667 41.660 41.667 41.660 41.667 ns 7,11,14 tr / tf 24mhz rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 11,13 tccj 24mhz cycle to cycle jitter 500 500 500 ps 11,14,15 ref tdc ref duty cycle 45 55 45 55 45 55 % 7,11,14 tperiod ref period 69.8413 71.0 69.8413 71.0 69.8413 71.0 ns 7,11,14 tr / tf ref rise and fall times 1.0 4.0 1.0 4.0 1.0 4.0 ns 11,13 tccj ref cycle to cycle jitter 1000 1000 1000 ps 11,14,15 ddr vx crossing point voltage of ddrt/c 0.5*v dd ? 0.2 0.5*v ddd + 0.2 0.5*v ddd ? 0.2 0.5*v ddd + 0.2 0.5*v ddd ? 0.2 0.5*v ddd +0.2 v19 vd differential voltage swing 0.7 v ddd + 0.6 0.7 v ddd + 0.6 0.7 v ddd + 0.6 v20 tdc ddrt/c(0:5) duty cycle 45 55 45 55 45 55 % 21 tperiod ddrt/c(0:5) period 9.85 10.2 14.85 15.3 9.85 10.2 ns 21 tr / tf ddrt/c(0:5) rise/fall slew rate 1 3 1 3 1 3 v/ns 13 tskew ddrt/c to any ddrt/c clock skew 100 100 100 ps 11,15,21 tccj ddrt/c(0:5) cycle to cycle jitter 75 75 75 ps 11,15,21 thpj ddrt/c(0:5) half-period jitter 100 100 100 ps 11,15,21 tdelay buf_in to any ddrt/c delay 1 4 1 4 1 4 ns 11,14 tskew fbout to any ddrt/cskew 100 100 100 ps 11,14 tstable all clock stabilization from power-up 333ms18 notes: 5. all outputs loaded as per maximum capacitive load table. 6. all outputs are not loaded. 7. this parameter is measured as an average over a 1- s duration, with a crystal center frequency of 14.31818 mhz. 8. this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within data sheet specifications. 9. when crystal meets minimum 40-ohm device series resistance specification. 10. measured between 0.2v dd and 0.7v dd . 11. all outputs loaded as per loading specified in the table 11. 12. when x in is driven from an external clock source (3.3v parameters apply). 13. probes are placed on the pins, and measurements are acquired between 0.4v and 2.4v for 3.3v signals and between 0.4v and 2.0 v for 2.5v signals, and between 20% and 80% for differential signals. 14. probes are placed on the pins, and measurements are acquired at 1.5v for 3.3v signals and at 1.25v for 2.5v, and 50% point f or differential signals. 15. this measurement is applicable with spread on or spread off. 16. probes are placed on the pins, and measurements are acquired at 2.4v for 3.3v signals and at 2.0v for 2.5v signals) 17. probes are placed on the pins, and measurements are acquired at 0.4v. 18. the time specified is measured from when all vdd ? s reach their respective supply rail (3.3v and 2.5v) till the frequency output is stable and operating within the specifications. 19. the typical value of vx is expected to be 0.5*vddd (or 0.5*vddc for cpucs signals) and will track the variations in the dc l evel of the same. 20. vd is the magnitude of the difference between the measured voltage level on a ddrt (and cpucs_t) clock and the measured volt age level on its complementary ddrc (and cpucs_c) one. 21. measured at vx, or where subtraction of clk-clk# crosses 0 volts. 22. see figure 10. for 0.7v loading specification. 23. measured from vol=0.175v to voh=0.525v. 24. measurements taken from common mode waveforms, measure rise/fall time from 0.41v to 0.86v. rise/fall time matching is define d as ? the instantaneous difference between maximum clk rise (fall) and minimum clk# fall (rise) time, or minimum clk rise (fall) and maximum clk# fall (rise) time ? . this parameter is designed for waveform symmetry. 25. measurement taken from differential waveform, from -0.35v to +0.35v. 26. measured in absolute voltage, i.e. single-ended measurement. 27. measured at vx between the rising edge and the following falling edge of the signal. 28. measured at vx between the falling edge and the following rising edge of the signal. 29. this parameter is intended to be 0.45*tperiod(min) for minimum spec. and 0.55*tperiod(min) for maximum spec. 30. determined as a fraction of 2*(trise-tfall)/(trise+tfall). ac parameters (continued) parameter description 100 mhz 133mhz 200 mhz unit notes [4] min. max. min. max min. max
CY28341 document #: 38-07367 rev. *a page 13 of 21 p4 processor selp4_k7# = 1 power-down assertion (p4 mode) when pd# is sampled low by two consecutive rising edges of cpu# clock then all clock outputs except cpu clocks must be held low on their next high to low transition. cpu clocks must be held with the cpu clock pin driven high with a value of 2 x iref, and cpu# undriven. note that figure 4 shows cpu = 133 mhz, this diagram and description is appli- cable for all valid cpu frequencies 66, 100, 133, 200mhz.due to the state of internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. pci 33mhz pw rdw n# cput 133mhz cput# 133mhz ref 14.318mhz usb 48mhz sdram 133mhz ddrt 133mhz ddrc 133mhz agp 66mhz figure 2. power-down assertion timing waveform (in p4 mode)
CY28341 document #: 38-07367 rev. *a page 14 of 21 rise and fall times power-down deassertion (p4 mode) the power-up latency needs to be less than 3 ms. amd k7 processor selp4_k7# = 0 power-down assertion (k7 mode) when the pd# signal is asserted low, all clocks are disabled to a low level in an orderly fashion prior to removing power from the part. when pd# is asserted (forced) low, the device transitions to a shutdown (power-down) mode and all power supplies may then be removed. when pd# is sampled low by two consecutive rising edges of cpu clock, then all affected clocks are stopped in a low state as soon as possible. when in power-down (and before power is removed), all outputs are synchronously stopped in a low state (see figure3 below), all pll ? s are shut off, and the crystal oscillator is disabled. when the device is shutdown, the i2c function is also disabled. pci 33mhz pw rdw n# cpu 133mhz cpu# 133mhz agp 66mhz ref 14.318mhz usb 48mhz <1.5 m sec sdram 133mhz ddrt 133mhz ddrc 133mhz figure 3. power-down deassertion timing waveform (in p4 mode)
CY28341 document #: 38-07367 rev. *a page 15 of 21 pci 33mhz pwrdwn# ref 14.318mhz usb 48mhz sdram 133mhz ddrt 133mhz ddrc 133mhz agp 66mhz cpuod_c 133mhz cpucs_c 133mhz cpuod_t 133mhz cpucs_t 133mhz figure 4. power-down assertion timing waveform (in k7 mode)
CY28341 document #: 38-07367 rev. *a page 16 of 21 power-down deassertion (k7 mode) when de-asserted pd# to high level, all clocks are enabled and start running on the rising edge of the next full period in order to guarantee a glitch-free operation, no partial clock pulses. note: 31. this time diagram shows that vtt_pwrgd# transits to a logic low in the first time at power-up. after the first high to low t ransition of vtt_pwrgd#, device is not affected, vtt_pwrgd# is ignored. pci 33mhz pw rdw n# cpu 133mhz cpu# 133mhz agp 66mhz ref 14.318mhz usb 48mhz <1.5 m sec sdram 133mhz ddrt 133mhz ddrc 133mhz figure 5. power-down deassertion timing waveform (in k7 mode) vid (0:3), sel (0,1) vtt_pw rgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 w ait for vtt_gd# sample sels off off on on state 1 (note a) figure 6. vtt_pwgd# timing diagram (with advanced piii processor selp4_k7 = 1 ) [31]
CY28341 document #: 38-07367 rev. *a page 17 of 21 connection circuit ddrt/c signals for open drain cpu output signals (with k7 processor selp4_k7# = 0) v t t p w r g d # = l o w delay 0.25m s s1 power off s0 vdda = 2.0v sample inputs fs(3:0) s2 vdd3.3 = off normal operation s3 w ait for 1.146m s enable outputes figure 7. clock generator power-up/ run state diagram (with p4 processor selp4_k7# = 1 ) measurement point measurement point 20 pf 20 pf 680 pf 680 pf 47 ohm 47 ohm 52 ohm 5" 52 ohm 5" cpuod_t cpuod_c vddcpu(1.5v) 500 ohm vddcpu(1.5v) 500 ohm 60.4 ohm 60.4 ohm 301 ohm 500 ohm 500 ohm 3.3v 3.3v 52 ohm 1 " 52 ohm 1" figure 8. 6? 6 ? figure 9.
CY28341 document #: 38-07367 rev. *a page 18 of 21 for differential cpu output signals (with p4 processor selp4_k7= 1) the following diagram shows lumped test load configurations for the differential host clock outputs. note: 32. ideally the probes should be placed on the pins. if there is a transmission line between the test point and the pin for one signal of the pair (e.g., cpu), the same length transmission line to the other signal of the pair (e.g., agp) should be added. table 10. signal loading table clock name max load (in pf) ref (0:1), 48mhz (usb), 24_48mhz 20 agp(0:2), sdram (0:11) 30 pci_f(0:5) 30 ddrt/c (0:5), fbout cput/c see figure 10 cpuod_t/c see figure 8 cpucs_t/c see figure 9 clk measurement point r ref r ta1 cput multsel clk measurement point r la1 r d r lb1 r la2 r lb2 r ta2 r tb1 r tb2 c la c lb t pcb t pcb cput# figure 10. table 11. lumped test load configuration component 0.7v amplitude value 1.0v amplitude value r ta1 , r ta2 33 ? 0 ? r la1 , r la2 49.9 ? t pcb 3 ? 50 ? z3 ? 50 ? z r lb1 , r lb2 63 ? r d 470 ? r tb1 , r tb2 0 ? 33 ? c la , c lb 2 pf 2 pf r ref 475 ? w/mult0 = 1 221 ? w/mult0 = 0 group timing relationships and tolerances [32] offset (ps) tolerance (ps) conditions t csagp cpucs to agp 750 500 cpucs leads t ap agp to pci 1,250 500 agp leads
CY28341 document #: 38-07367 rev. *a page 19 of 21 0ns 10ns 20ns 30ns agp clock 66.6mhz pci clock 33.3mhz cpu clock 66.6mhz cpu clock 100mhz cpu clock 133.3mhz t ap t csagp ordering information part number package type product flow CY28341oc 56-pin shrunk small outline package (ssop) commercial, 0 to 70 c CY28341oct 56-pin shrunk small outline package (ssop) ? tape and reel commercial, 0 to 70 c CY28341zc 56-pin thin shrunk small outline package (tssop) commercial, 0 to 70 c CY28341zct 56-pin thin shrunk small outline package (tssop) ? tape and reel commercial, 0 to 70 c
CY28341 document #: 38-07367 rev. *a page 20 of 21 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package drawing and dimensions purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. via is a trademark of via technologies, inc. pentium 4 is a registered trademark of intel corporation. a thlon is a trademark of amd corporation, inc. dial-a-frequency, dial-a-db, dial-a-skew, and dial-a-ratio are trademarks of cypress semiconductor. all product and computer names mentioned in this document may be the trademarks of their respective holders. 51-85060-b 56-lead thin shrunk small outline package, type ii (6 mm 12 mm) z56 56-lead shrunk small outline package o56 51-85062-c
CY28341 document #: 38-07367 rev. *a page 21 of 21 document title: CY28341 universal single-chip clock solution for via p4m266/km266 ddr systems document number: 38-07367 rev. ecn no. issue date orig. of change description of change ** 112783 05/28/02 dmg new data sheet *a 122908 12/26/02 rbi add power requirements to maximum ratings information

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